For increasing the integration density as well as improving the performances of semiconductor devices, development of finer structures has been achieved for the MISFETs constituting the semiconductor device. However, since the finer structure of the MISFET increases the influence by the short-channel effect thereof, it is an important subject to reduce the short-channel effect. Among other proposals for the suppression of the short-channel effect based on the technique in accordance with a so-called scaling rule, a proposal uses a reduced thickness of the gate insulation film. This technique suppresses the short-channel effect by reducing the thickness of the gate insulation film, in order to easily control the depletion layer formed in the Si substrate while applying a voltage to the gate insulation film.
However, if the gate electrode of the MISFET is made from polysilicon doped with impurities, there occurs a phenomenon that the depletion layer is formed also in the gate electrode in the case where the electric field applied to the gate electrode is relatively stronger due to the thickness reduction of the gate insulation film. This results in a larger effective thickness of the gate insulation film.
For solving this depletion problem of the gate electrode, there is a proposal that the gate electrode should be made from a metallic material. The metal gate made from the metallic material has the advantages of reduction in the resistance of the gate electrode and suppression of boron penetration, in addition to the advantage of above suppression of the gate electrode. Thus, the metal gate made of Al, W, WTi or nitride thereof was used in the initial stage of development of the MIS semiconductor devices.
However, there are following problems in the metal gate. For example, since Al has a melting point of as low as about 660 degrees C., a heat treatment at a temperature of equal to or above 400 degrees C., if performed for the purpose of activation of the source and drain, raises the problems of disconnection of the gate electrode and diffusion of the Al atoms into the peripheral area. In addition, there is a problem in that W changes the characteristic thereof due to oxidation. Furthermore, there is problem in that W and WTi have lower resistances against cleaning and are dissolved during an acid cleaning treatment.
Assuming that the gate electrode is made of a TiN film, for example, which is controlled in the alignment thereof, the work function of the gate electrode is improved in the reproducibility thereof. Thus, study for using the TiN as the gate electrode material has been conducted, as described in Patent Publication JP-A-2001-15756, for example. However, since the work function of the TiN is around 4.6 eV, and thus resides in the vicinity of midgap of silicon, i.e., in the intermediate value between the Ec and the Ev of the silicon substrate, both the N-type MISFET and P-type MISFET have higher threshold voltages (Vth). More specifically, a finer structure of the device employed in accordance with the scaling rule, the power dissipation will increase. Although it is generally effective to reduce the power supply voltage for reduction of the power dissipation, the threshold voltage must be reduced accordingly. If the metal gate is made of TiN, the threshold voltage (Vth) is excessively high for the MISFET of a sub-100-nm gate-length generation, as a result of which there arises the problem that the current driveability thereof is decreased.
In view of the above, metal gate materials for the N-type MISFET and P-type MISFET are desired which are capable of suppressing the thresholds of the N-type MISFET and P-type MISFET. It is impossible to significantly change the work function of the metal by adjusting the impurity concentration thereof, unlike the polysilicon. Thus, for changing the threshold of the metal gate, it is necessary to employ different kinds of metals configuring the gate electrode. Examples of the proposed metallic materials having work functions around 4 eV suited to the gate metal of the N-type MISFET (hereinafter referred to as N-type MIS metal) include Hf, Zr, Al, Ti, Ta and Mo. Examples of the metallic materials having work functions around 5 eV suited to the P-type MISFET (referred to as P-type MIS metal) include RuO2, WN, Ni, Ir, Mo2N, TaN and Pt. Table 1 tabulates the work functions of metals recited in literatures. The work functions shown in Table 1 are values recited in literature “Applied Physics, vol. 69, No. 1 (2000), pp 4-14”, literature “Journal of Vacuum Science and Technology B16(2) pp. 829 (1998) etc. Satisfactorily lower threshold voltages can be obtained for both the N-type MISFET and P-type MISFET by a combination of one of the above metallic materials selected as the gate electrode material for the N-type MISFET and one of the above metallic materials selected as the gate electrode material for the P-type MISFET.
TABLE 1Metal Gate MaterialWork Function (eV)Hf3.9Zr4.05ZrN4.7Al4.08Ti4.17Ta4.19Mo4.2W4.52TiN4.7Ru4.71RuO24.9WN5.0Ni5.15Ir5.27Mo2N5.33TaN5.41Pt5.65
However, it is very difficult to manufacture a device including such N-type MISFET and P-type MISFET by using a conventional technique for manufacturing the device. The reasons therefor will be described hereinafter. For differentiating the gate electrodes of the N-type MISFET and P-type MISFET in the fabrication, it is necessary to form an N-type MIS metallic film on the substrate, detach the N-type MIS metallic film in the area for forming therein the P-type MISFET and form a P-type MIS metallic film therein. However, since the metal for configuring the gate electrode must be chemically stable, the metal is difficult to etch accordingly and is likely to damage the gate oxide film. In the submicron MISFETs, since the gate oxide film has a thickness of 2 nm or less, it is very difficult to detach the N-type MIS metallic film without damaging the gate oxide film, and also difficult to reform a gate oxide film having an excellent property. In addition, since different kinds of metals configuring the gate electrodes need different process conditions, there arise the problems of complex adjustments of the process conditions as well as impossibility of employing common process conditions. Further, these metals must satisfy a variety of conditions such as excellent resistance against the cleaning accompanied by detachment of the gate metal, effective prevention of channeling during ion implantation after configuration of the gate electrodes, stability of interface between the gate electrode and the gate oxide film during a heat treatment reaching up to a temperature of about 1000 degrees C. etc.
Another technique in accordance with the scaling rule is known which forms dummy gate electrodes on the gate oxide film of the P-type MISFETs, deposits a metallic film over an entire area for use as the gate electrodes of the N-type MISFETs, removes the dummy gate electrodes and deposits another metallic film on the gate oxide film of the P-type MISFETs for use as the gate electrodes of the P-type MISFETs. This technique also includes the step of removing the dummy gate electrodes formed on the gate insulation film, and damages the gate insulation film in the process.
Thus, a technique using a damascene process is proposed for solving the problems accompanied by the etching of the gate electrode and the heat treatment for activating the source and drain. Patent Publication JP-A-2000-315789, for example, describes in the first embodiment thereof the technique as detailed below. A HfO2 film is formed as a gate insulation film in the trenches of gate portions of the N-type MISFET and P-type MISFET formed as depressions, followed by forming a HfN film. Thereafter, the portion other than the gate electrodes of the P-type MISFETs is protected by a resist, followed by selectively removing the HfN film on the gate electrode portions of the P-type MISFETs by using a hydrogen peroxide solution. Subsequently, a Co film is deposited in the entire area. This provides layered films including HfN film and Co film for the gate electrodes of the N-type MISFETs, whereas a single Co film for the gate electrodes of the P-type MISFETs. Thus, two kinds of different gate electrodes can be formed for the N-type MISFETs and P-type MISFETs. The HfN film has a small thickness of around 10 nm for the purpose of preventing the etching from proceeding in the lateral direction during the etching removal of the HfN film. JP-A-2000-315789 recites that such a structure provides lower threshold voltages for both the N-type MISFETs and P-type MISFETs.
However, since the threshold voltage of the MISFET is strongly affected by the situation of the electrons in the interface between the gate insulation film and the gate electrode, the threshold voltage of the MISFET varies widely to cause a lower product yield of the semiconductor devices unless the HfN film formed in the trenches is completely removed. The complete removal of the HfN film and the protection of the gate insulation film are tradeoffs and thus very difficult to be compatible. Furthermore, the two kinds of gate electrodes, if formed by the damascene process, raises the problem of complicating the process to increase the fabrication cost and reduce the product yield.
For solving the problems of detachment of the metallic film as described before, another technique is proposed which uses ion-implantation of nitrogen into a Mo film. For example, Qiang Lu et al. disclose a technique for depositing a Mo film for use as the gate electrodes of the N-type MISFET and P-type MISFET, followed by controlling the work function of the P-type MISFET by ion-implantation of nitrogen into only the gate electrode of the P-type MISFET. Using this technique, the absence of the step of detaching the gate electrode in contact with the gate insulation film solves the problem of complicated process accompanied by the detachment of the metal and the wide range of variation of the threshold.
However, the above conventional technique involves the problems as shown hereinafter. In the technique of ion-implantation of nitrogen into the Mo film, the pure metal, Mo, in direct contact with the silicon oxide film in the N-type MISFET raises the problem of degradation of the thermal stability of the interface. In addition, the ion-implantation of nitrogen into the Mo film allows the nitrogen to be introduced also into the silicon oxide film, or gate insulation film, thereby involving the problem of degrading the long-term reliability of the gate insulation film.